sci-electronics/adms
ADMS is a code generator for the Verilog-AMS language
ChangeLog
commit f72458bfa125ee181109299fc8dcd25726715f55
Author: Sergey Alirzaev <zl29ah@gmail.com>
Date: Wed Jul 18 15:26:23 2018 +0300
+ adms: new ebuild
Author: Sergey Alirzaev <zl29ah@gmail.com>
Date: Wed Jul 18 15:26:23 2018 +0300
+ adms: new ebuild